This invention relates to a switched capacitor circuit which constitutes an input signal integrating circuit together with a charge accumulator.
The input signal integrating circuit involves a switched capacitor circuit and a charge accumulator. The switched capacitor circuit is provided with at least one switch and at least one capacitor, and supplies a charge generated by an input signal to a charge accumulator. An output signal from the charge accumulator is delivered to another circuit. The above-mentioned input signal integrating circuit is widely accepted in the form of monolithic IC for the manufacture of a precise filter, A/D converter, and D/A converter. When one tries to fabricate a filter involving unit circuits each including a switched capacitor circuit and a charge accumulator, it is necessary to preset the time constant of a circuit composed of the unit circuits at a predetermined level in order to define the frequency characteristics of the filter.
A switched capacitor circuit is so designed as to control the charge or discharge of a capacitor by rendering switches conducting or nonconducting. An output signal from the switched capacitor circuit is transmitted to a charge accumulator. The time constant of, for example, an integrator composed of the capacitor and accumulator is defined by a product obtained by multiplying the ratio Co/C.sub.Q (hereinafter referred to as "a capacitance ratio") by the switching period (T). The capacitance C.sub.Q represents the switched capacitor capacitance and Co represents the accumulator capacitor capacitance. When, therefore, a reciprocal 1/fc of the filter cut-off frequency fc is tremendously larger than the switching period or when C.sub.Q of the filter has a large value, then aforementioned capacitor ratio Co/C.sub.Q should be very much increased.
When, in the case of the monolithic IC, the above-mentioned capacitor ratio is determined by the capacitors formed on a semiconductor chip, the precision of the capacitor ratio is further deteriorated as the capacitance of the capacitor C.sub.Q of the switched capacitor circuit is reduced. This event arises from problems occurring in the manufacture of IC's. Namely, the capacitance of a unit capacitor formed on a chip is defined by the IC-manufacturing technique. To attain the predetermined capacity ratio, therefore, it is necessary to use for the accumulator the capacitor whose capacitance has a value arrived at by multiplying the capacitance of the unit capacitor by the aforesaid predetermined capacity ratio. If, therefore, it is attempted to attain a large capacity ratio, the total sum of capacitances of the capacitors will be enormously enlarged, thus causing the capacitors to occupy a large area on the chip.
In view of the above-mentioned technical circumstances, a process has been developed which is designed to reduce the equivalent capacitance of the capacitors involved in a switched capacitor circuit (the capacitance of the switched capacitor circuit defining the capacitance ratio). An article entitled "A method of equivalent circuit transformation on a Switched Capacitor Filter" appears in a collection of manuscripts of lectures given at the national convention (1981) of the information system department of the Institute of Electronics and Communication Engineers of Japan. The article sets forth means for increasing the capacitor ratio of a filter by connecting three capacitors in ladder form.
Description may now be made of the summary of the article with reference to FIG. 1.
First and second switches 2a, 2b are connected between input signal terminal 1 and the ground. Third and fourth switches 2c, 2d are connected between output terminal 4 (connected, for example, to a charge accumulator) and the ground. Serial capacitors 3a, 3b are connected between the junction of switches 2a, 2b and the junction of switches 2c, 2d. Capacitor 3c is connected between the junction of capacitors 3a, 3b and the ground. Switch 2e is connected in parallel to capacitor 3c. Now let it be assumed that switches 2a, 2d are rendered conducting, and switched 2b, 2c, 2e are rendered nonconducting, thereby charging capacitors 3a, 3b, 3c. Then 2a, 2d are rendered nonconducting and switches 2b, 2c, 2e are rendered conducting, thereby short circuiting capacitors 3a, 3c. Then the electric charge of capacitor 3b alone is transmitted, for example, to a charge accumulator connected to terminal 4. The above-mentioned process offers the advantage that the equivalent capacitance of a switched capacitor circuit contributing to the determination of the aforementioned capacity ratio reaches a value (Ca+Cb+Cc)/Ca which results when capacitor 3a alone is used. As a result, the total capacity required to obtain the predetermined capacity ratio is noticeably decreased. In this case, Ca, Cb, Cc respectively represent the capacitances of the capacitors 3a, 3b, 3c.
The conventional switched capacitor circuit shown in FIG. 1 is accompanied with the undermentioned drawbacks. Namely, switches 2a to 2e are formed of MOS FETs. As seen from FIG. 2, the MOS FET has stray capacitances Cgd, Cgs, Cdb and Csb between the electrodes of gate G, drain D, source S, and back gate B (substrate). These stray capacitances exert the undermentioned harmful effect on a switched capacitor circuit. To begin with, these stray capacitances give rise to an error in the aforementioned capacitance ratio. In the second place, a clock signal supplied to the gate G leaks into the switched capacitor circuit through stray capacitances Cgs, Cgd. When the leaked signal is brought into the switched capacitor circuit of the succeeding filter connected to a filter involving the switched capacitor circuit FIG. 1, and is subjected to sampling by the same frequency as that of the preceding filter, then a D.C. component is sometimes generated in the succeeding filter. In the third place, noises resulting from the power source leak from back gate B into the switched capacitor circuit through stray capacitances Cdb, Csb. These noises, even if composed of a frequency component falling outside of the frequency zone of an input signal, tend to be changed in the switched capacitor circuit into noises possessing a frequency component falling within the input signal frequency zone, thus deteriorating the S/N ratio of the filter circuit. Particularly since the capacitor circuit and the circuit for producing a switch-controlling clock signal are formed in the same chip, the power source is contaminated by noises having tremendously high frequency components.